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CXD2470R
Timing Generator for Frame Readout CCD Image Sensor
Description The CXD2470R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX224,ICX284,ICX202 and ICX232 CCD image sensor. Features * Base oscillation frequency 24.00 to 36.00MHz (max.) * High-speed/low-speed shutter function * Supports quadruple-speed readout drive * Horizontal driver for CCD image sensor * Vertical driver for CCD image sensor Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX224 (Type 1/2, 2020K pixels) ICX284 (Type 1/2.7, 2020K pixels) ICX202 (Type 1/3, 1250K pixels) ICX232 (Type 1/3.6, 1250K pixels) Pin Configuration
MCKO OSCO OSCI VDD5 VSS6 CKO SEN SCK HDI VDI CKI SSI
48 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.3 to +7.0 V -10.0 to VSS V VL VH VL - 0.3 to +26.0 V VSS - 0.3 to VDD + 0.3 V * Input voltage VI * Output voltage VO1 VSS - 0.3 to VDD + 0.3 V VO2 VL - 0.3 to VSS + 0.3 V VO3 VL - 0.3 to VH + 0.3 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDDb 3.0 to 5.5 VDDa, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL -7.0 to -8.0 * Operating temperature Topr -20 to +75
V V V V V C
36 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 37 38 39 40 41 42 43 44 45 46 47 48 1 VSS1
35
34
33
32
31
30
29
28
27
26
25 24 VSS5 23 ADCLK 22 OBCLP 21 VSS4 20 CLPDM 19 PBLK 18 XRS 17 XSHD 16 XSHP 15 VDD4 14 VDD3 13 H2
Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
2 RST
3 DSGAT
4 ID
5 WEN
6 EBCKSM
7 VDD1
8 VDD2
9 RG
10 VSS2
11 VSS3
12 H1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98Y31C9Z-PS
CXD2470R
Block Diagram
XSHD
VDD3
VDD2
XSHP
VDD4
VSS3
VSS2
14 12 13 11 OSCI OSCO 28 27
8
9
10
15 16 17 18 21
XRS
RG
H1
H2
VSS4 19 PBLK 20 CLPDM 22 OBCLP 23 ADCLK 24 VSS5 4 5 ID WEN 41 V1A 43 V1B 39 V2 44 V3A 46 V3B 40 V4 47 SUB 42 VH 38 VM 45 VL
CKI
26 Pulse Generator 1/2
CKO 25 MCKO 30
SSI 31 SCK 32 SEN 33 EBCKSM 6 V Driver 7 Register
VDD1
VDD5 29
VSS1
1
VSS6 36 3 DSGAT 2 RST 37 48 TEST1 TEST2 35 HDI 34 VDI
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CXD2470R
Pin Description Pin No. 1 2 Symbol VSS1 RST I/O -- I GND Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side Control input used to stop pulse generation. High: Normal operation, Low: Stop control Schmitt trigger input/No protective diode on power supply side Vertical direction line identification pulse output. Memory write timing pulse output. CHKSUM enable. High: Sum check invalid, Low: Sum check valid With pull-down resistor Description
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DSGAT ID WEN EBCKSM VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5 CKO CKI OSCO OSCI VDD5 MCKO
I O O I -- -- O -- -- O O -- -- O O O O O -- O O -- O I O I -- O
3.3V power supply. (Power supply for common logic block) 3.3V power supply. (Power supply for RG) CCD reset gate pulse output. GND GND CCD horizontal register clock output. CCD horizontal register clock output. 3.3 to 5.0V power supply. (Power supply for H1/H2) 3.3V power supply. (Power supply for CDS block) CCD precharge level sample-and-hold pulse output. CCD data level sample-and-hold pulse output. Sample-and-hold pulse output for analog/digital conversion phase alignment. Pulse output for horizontal and vertical blanking period pulse cleaning. CCD dummy signal clamp pulse output. GND CCD optical black signal clamp pulse output. Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. GND Inverter output. Inverter input. Inverter output for oscillation. Inverter input for oscillation. 3.3V power supply. (Power supply for common logic block) System clock output for signal processing IC. -3- When not used, leave open or connect a capacitor. When not used, fix low.
CXD2470R
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol SSI SCK SEN VDI HDI VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2
I/O I I I I I -- I -- O O O -- O O -- O O I
Description Serial interface data input for internal mode settings. Schmitt trigger input/No protective diode on power supply side Serial interface clock input for internal mode settings. Schmitt trigger input/No protective diode on power supply side Serial interface strobe input for internal mode settings. Schmitt trigger input/No protective diode on power supply side Vertical sync signal input. Horizontal sync signal input. GND IC test pin 1; normally fixed to GND. GND (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output. CCD vertical register clock output. -7.5V power supply. (Power supply for vertical driver) CCD vertical register clock output. CCD electronic shutter pulse output. IC test pin 2; normally fixed to GND. With pull-down resistor With pull-down resistor Schmitt trigger input Schmitt trigger input
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CXD2470R
Electrical Characteristics DC Characteristics Item Supply voltage 1 VDD2 Supply voltage 2 VDD3 Supply voltage 3 VDD4 Supply voltage 4 VDD1, VDD5 Pins Symbol VDDa VDDb VDDc VDDd (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd Typ. 3.3 3.3 3.3 3.3 Max. 3.6 5.5 3.6 3.6 Unit V V V V V 0.2VDDd V 0.7VDDd V 0.3VDDd V 0.7VDDd V 0.3VDDd V Feed current where IOH = -22.0mA VDDb - 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = -3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = -3.3mA VDDc - 0.8 0.4 VDDb - 0.8 0.4 0.4 V V V V V V V 0.4 10.0 -5.0 5.0 -7.2 5.4 -4.0 V mA mA mA mA mA mA
RST, DSGAT, Vt+ 1 SSI, SCK, Input voltage 1 SEN, Vt- EBCKSM TEST1, Input voltage 22 TEST2 Input voltage 3 VDI, HDI VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2
Output voltage 1
H1, H2
Output voltage 2
RG
Output voltage 3
XSHP, XSHD, VOH3 XRS, PBLK, OBCLP, CLPDM, VOL3 ADCLK CKO, MCKO VOH4 VOL4 IOL
Pull-in current where IOL = 2.4mA Feed current where IOH = -10.4mA VDDd - 0.8 Pull-in current where IOL = 7.2mA V1A/B, V2, V3A/B, V4 = -8.25V V1A/B, V2, V3A/B, V4 = -0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = -8.25V SUB = 14.75V
Output voltage 4
Output current 1
V1A, V1B, V3A, V3B, V2, V4
IOM1 IOM2 IOH
Output current 2
SUB
IOSL IOSH
1 These input pins are Schmitt trigger inputs and do not have protective diodes on the internal power supply side. 2 These input pins have internal pull-down resistors. Note) The above table indicates the condition for 3.3V drive.
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CXD2470R
Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI Symbol LVth VIH VIL VOH VOL RFB f Conditions
(Within the recommended operating conditions) Min. Typ. VDDd/2 0.7VDDd 0.3VDDd Max. Unit V V V V 0.4 500k 20 2M 5M 50 V MHz
OSCO OSCI, OSCO OSCI, OSCO
Feed current where IOH = -3.6mA Pull-in current where IOL = 2.4mA VIN = VDDd or VSS
VDDd - 0.8
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = -7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V
Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1F or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. -6-
CXD2470R
Switching Waveforms
TTMH 90%
TTHM VH 90%
V1A (V1B, V3A, V3B)
TTLM
10% 90%
10% 90%
TTML
VM
10%
10%
VL
TTLM 90% V2 (V4) 10% 90%
TTML
VM
10%
VL
TTLH 90% 90%
TTHL
VH
SUB
10%
10% VL
Waveform Noise
VH VCMH VCML
VCLH VCLL VL
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CXD2470R
Measurement Circuit
Serial interface data CKI C6
VDI HDI +3.3V -7.5V +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 37 R1 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 C2 C1 C2 R1 C2 R2 C3 C1 C2 C2 C1 C2 C2 R1 38 39 40 41 42 43 44 R1 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 CXD2470R 24 23 22 21 20 19 18 17 16 15 14 13 C5 C6 C6 C6 C6 C6 C6 C6 C6
C2 C2
R1
C4
C5
C1 R1
3300pF 30
C2 R2
560pF 10
C3
820pF
C4
30pF
C5
180pF
C6
10pF
-8-
CXD2470R
AC Characteristics AC characteristics between the serial interface clocks
0.8VDDd SSI SCK SEN SEN ts2 0.2VDDd 0.8VDDd ts1 0.2VDDd ts3 0.8VDDd th1
(Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 80 20 Typ. Max. Unit ns ns ns ns
ts1 th1 ts2 ts3
Serial interface clock internal loading characteristics (1)
Example: During frame mode VDI HDI V1A Enlarged view
HDI V1A
0.2VDDd
ts1 0.8VDDd SEN
th1 0.2VDDd
Be sure to maintain a constantly high SEN logic level near the falling edge of the HDI in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HDI SEN hold time, activated by the falling edge of HDI -9- Min. 0 102 Typ. Max. Unit ns s
ts1 th1
CXD2470R
Serial interface clock internal loading characteristics (2)
Example: During frame mode VDI HDI Enlarged view
VDI HDI
0.2VDDd
ts1 SEN 0.8VDDd
th1 0.2VDDd
Be sure to maintain a constantly high SEN logic level near the falling edge of VDI. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of VDI SEN hold time, activated by the falling edge of VDI Min. 0 200 Typ. Max. Unit ns ns
ts1 th1
Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2470R at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD2470R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDd
Output signal tpdPULSE
(Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns
tpdPULSE Output signal delay, activated by the rising edge of SEN
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CXD2470R
RST loading characteristics
RST
0.8VDDd 0.2VDDd tw1
(Within the recommended operating conditions) Symbol Definition RST pulse width Min. 35 Typ. Max. Unit ns
tw1
VDI and HDI loading characteristics
VDI, HDI
0.2VDDd ts1 0.8VDDd th1
0.2VDDd
MCKO
MCKO load capacitance = 10pF1 (Within the recommended operating conditions) Symbol Definition VDI and HDI setup time, activated by the rising edge of MCKO VDI and HDI hold time, activated by the rising edge of MCKO Min. 20 5 Typ. Max. Unit ns ns
ts1 th1
Output timing characteristics using DSGAT
DSGAT H1, H2, RG, XSHP, XSHD, XRS, ADCLK, PBLK, CLPDM, OBCLP
0.2VDDd 0.2VDDd tpDSGAT
H1 and H2 load capacitance = 180pF, RG load capacitance = 30pF, XSHP, XSHD, XRS, PBLK, CLPDM, OBCLP and ADCLK load capacitance = 10pF (Within the recommended operating conditions) Symbol tpDSGAT Definition Time until the above outputs go low after the fall of DSGAT Min. Typ. Max. 100 Unit ns
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CXD2470R
Output variation characteristics
MCKO
0.8VDDd
WEN, ID tpd1
WEN and ID load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 20 Typ. Max. 60 Unit ns
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CXD2470R
Description of Operation Pulses output from the CXD2470R are controlled mainly by the RST and DSGAT pins and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS1 RST DSGAT ID WEN ACT ACT ACT ACT ACT ACT L L ACT CAM SLP STB DSGAT RST -- ACT ACT L L ACT -- -- ACT L L -- -- ACT ACT L L L L -- -- ACT ACT ACT ACT ACT L L L L L L L L L L -- ACT ACT L L L L -- L L H ACT L L L L L ACT ACT ACT H H L L ACT ACT L ACT ACT L ACT ACT ACT L ACT L L ACT Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKO CKI OSCO OSCI VDD5 MCKO SSI SCK SEN VDI HDI VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 ACT ACT VH VH ACT ACT VH VH ACT ACT ACT VM VM VH ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT CAM ACT ACT ACT ACT SLP ACT ACT ACT ACT STB DSGAT RST L ACT ACT ACT -- L ACT ACT ACT ACT ACT -- -- -- VM VM VH -- VH VH -- VH VH -- VH VH VL VL VH VH VM VL VM VM VH VM VL VM ACT ACT ACT ACT ACT ACT ACT DIS DIS DIS ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT
EBCKSM ACT VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5
Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45), respectively, in the controlled status.
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CXD2470R
Serial Interface Control The CXD2470R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HDI. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VDI or the rising edge of SEN.
SSI SCK SEN
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
There are two categories of serial interface data: CXD2470R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below.
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CXD2470R
Control Data Data D00 to D07 D08 to D09 D10 to D11 D12 D13 to D14 D15 to D35 D36 to D37 D38 to D39 D40 to D47 LDAD Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 0 All 0 All 0 1 ADCLK logic phase switching See D36 to D37 LDAD. 0 STB Standby control See D38 to D39 STB. All 0 All 0
10000001 Enabled Other values Disabled
CTG
Category switching
See D08 to D09 CTG.
MODE CCD SMD
Drive mode switching CCD switching Electronic shutter mode switching
See D10 to D11 MODE. ICX224/ICX284 ICX202/ICX232
See D13 to D14 SMD.
--
--
--
--
CKSM
Check sum bit
See D40 to D47 CKSM.
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CXD2470R
Shutter Data Data D00 to D07 D08 to D09 D10 to D17 D18 to D27 D28 to D35 D36 to D39 D40 to D47 CKSM Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 All 0 All 0
10000001 Enabled Other values Disabled
CTG
Category switching
See D08 to D09 CTG.
SVD
Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification
See D10 to D17 SVD.
SHD
See D18 to D27 SHD.
SPL
See D28 to D35 SPL.
--
--
--
--
Check sum bit
See D40 to D47 CKSM.
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CXD2470R
Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD2470R by the serial interface, the CXD2470R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 1 D08 0 1 0 1 Description of operation Loading to control data register Loading to shutter data register Test mode
Note that the CXD2470R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied.
Shared data: D40 to D47 CKSM [Check sum] These are the check sum bits. Apply the data shown below. This function is valid when EBCKSM (Pin 6) is low. MSB D07 D15 D23 D31 D39 +) D47 0 LSB D00 D08 D16 D24 D32 D40 0
D06 D14 D22 D30 D38 D46 0
D05 D13 D21 D29 D37 D45 0
D04 D12 D20 D28 D36 D44 0
D03 D11 D19 D27 D35 D43 0
D02 D10 D18 D26 D34 D42 0
D01 D09 D17 D25 D33 D41 0
CKSM Reflected when the total is "0".
Control data: D10 to D11 MODE [Drive mode] The CXD2470R drive mode can be switched as follows. However, the drive mode bits are loaded to the CXD2470R and reflected at the falling edge of VDI. D11 0 0 1 1 D10 0 1 0 1 Description of operation Quadruple-speed mode (default) Frame mode (A field readout) Frame mode (B field readout) Frame mode
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CXD2470R
Control data: D12 CCD [CCD switching] Specifies CCD image sensor to be used. However, the CCD image sensor switching bit is loaded to the CXD2470R and reflected at the falling edge of VDI. The default is "ICX224/ICX284". D12 0 1 CCD ICX224/ICX284 ICX202/ICX232
Control data: D36 to D37 LDAD [ADCLK logic phase adjustment] This indicates the ADCLK logic phase adjustment data. The default is 90 relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment () 0 90 180 270
Control data: D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD2470R and control is applied immediately at the rising edge of SEN. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode
See the Pin Status Table for the pin status in each mode.
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CXD2470R
Control data/shutter data: [Electronic shutter] The CXD2470R realizes various electronic shutter functions by using control data D13 to D14 SMD and shutter data D10 to D17 SVD, D18 to D27 SHD and D28 to D35 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 to D14 SMD. D14 0 0 1 1 D13 0 1 0 1 Description of operation Electronic shutter stopped mode High-speed/low-speed shutter mode HTSG control mode
The electronic shutter data is expressed as shown in the table below using D18 to D27 SHD as an example. MSB D27 D26 0 1 1 D25 1 D24 1 C D23 0 D22 0 D21 0 D20 0 3 D19 1 LSB D18 1 SHD is expressed as 1C3h .
[Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D17 D18 to D27 D28 to D35 Description Number of vertical periods specification (00h SVD FFh) Number of horizontal periods specification (000h SHD 3FFh) Vertical period specification for high-speed shutter operation (00h SPL FFh)
The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying high-speed shutter, SVD is set to "00h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "01h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses - 1). Note) The bit data definition area is assured in terms of the CXD2470R functions, and does not assure the CCD characteristics.
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CXD2470R
VDI
SHD
SVD
V1A SUB WEN SMD SVD SHD 01 02h 10Fh 01 00h 050h
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL VDI SHD V1A SUB WEN SMD SPL SVD SHD 10 01h 02h 10Fh 01 00h 00h 0A3h SVD
Incidentally, SPL is counted as "00h", "01h", "02h" and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa.
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CXD2470R
[HTSG control mode] During this mode, all shutter data items are invalid. The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure.
VDI
V1A SUB Vck WEN SMD 01 11 01 Exposure time
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Chart-1
* ICX224/ICX284
Vertical Direction Timing Chart
MODE Frame mode
A Field B Field
Applicable CCD image sensor
VDI
25 31 24 31 (651) 650 1
(1300) 650 1
HDI
SUB A C B
C
V1A
V1B
V2
V3A
1228
1230
1232
1234
1236
1225
1227
1229
1231
1233
PBLK
OBCLP
CLPDM
ID
WEN
CXD2470R
The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
1235
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1 3 5 7 9 1 3 5 7 9 11 13 15 17 19 21
V3B
V4
2 4 6 8 10 2 4 6 8 10 12 14 16 18
CCD OUT
Chart-2
* ICX224/ICX284
Vertical Direction Timing Chart
MODE Quadruple-speed mode
Applicable CCD image sensor
VDI
12 16 325 1 12 16
325 1
HDI
SUB D D
V1A
V1B
V2
V3A
1218
1223
1226
1215
1218
1223
1226
1231
1210
1215
1231
PBLK
OBCLP
CLPDM
ID
WEN
1234
CXD2470R
The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
1234
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4 9 2 7 10 15 18 23 26 31 34 39 42 47 50 55 58
V3B
V4
4 9 2 7 10 15 18 23 26 31 34 39 42 47 50 55
CCD OUT
Chart-3 Frame mode
* ICX224/ICX284
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
(1848) 0 50 100 150 200 250
HDI
MCKO
56 188
H1
H2
72 120
V1A/B
104 152
V2
56 136
V3A/B
88 168
V4
88 152
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56 51 104 104
SUB
214
PBLK
13
OBCLP
190 214
CLPDM
ID
WEN
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-1.
CXD2470R
Chart-4
* ICX224/ICX284
Horizontal Direction Timing Chart
MODE Quadruple-speed mode
Applicable CCD image sensor
(1848) 0 50 100 150 200 250
HDI
MCKO
56 188
H1
H2
56 88 120 152
V1A/B
72 104 136 168
V2
56 88 120 152
V3A/B
72 104 136 168
V4
88 152
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56 51 104 104
SUB
214
PBLK
13
OBCLP
190 214
CLPDM
ID
WEN
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-2.
CXD2470R
Chart-5
* ICX224/ICX284
Horizontal Direction Timing Chart (High-speed sweep: C)
MODE Frame mode
Applicable CCD image sensor
(1848) 0 50 100 150 200 250
HDI
MCKO
56 188
H1
H2
56 84 112 140 168 196 224 252 280
V1A/B
70 182 98 126 154 210 238 266
V2
56 84 112 140 168 196 224 252 280
V3A/B
70 98 126 154 182 210 238 266
V4 #1
88 152
- 26 -
#2
56 51
#3
#4
SUB
PBLK
13
OBCLP
CLPDM
ID
WEN
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 22H of 1848ck (#758).
CXD2470R
Chart-6
* ICX224/ICX284
Horizontal Direction Timing Chart
MODE Frame mode
Applicable CCD image sensor
1027 1029
1071
1091
1131 1133
(1848) 0 (1848) 0
56 72 88 104 120 136 152 168 184 200 216
1175
56 72 88 104 120 136 152 168
HDI [A]
[A Field]
V1A
V1B
V2
V3A
V3B
- 27 -
[B] Logic alignment portion
V4
[B Field]
V1A
V1B
V2
V3A
V3B
V4
CXD2470R
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s).
Chart-7 Quadruple-speed mode
* ICX224/ICX284
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
1071
1027 1029
1091
1131 1133
(1848) 0 1111 (1848) 0
56 72 88 104 120 136 152 168
1175
56 72 88 104 120 136 152 168
HDI [D]
V1A
V1B
- 28 -
V2
V3A
V3B
V4
CXD2470R
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s).
Chart-8
* ICX/202/ICX232
Vertical Direction Timing Chart
MODE Frame mode
A Field B Field
Applicable CCD image sensor
VDI
37 40 (526) 525 1 36 40
(1050) 525 1
HDI
SUB E G F
G
V1A
V1B
V2
V3A
958
960
962
964
966
955
957
959
961
963
CCD OUT
PBLK
OBCLP
CLPDM
ID
WEN
CXD2470R
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
965
- 29 -
1 3 1 3 5 7 9 11 13 15 17 19 21 23
V3B
V4
2 4 2 4 6 8 10 12 14 16 18 20
Chart-9
* ICX202/ICX232
Vertical Direction Timing Chart
MODE Quadruple-speed mode
Applicable CCD image sensor
VDI
17 20 262 1 17 20
262
1
HDI
SUB H H
V1A
V1B
V2
V3A
949
952
957
960
965
944
949
952
957
960
CCD OUT
1 4 5 8 13 16 21 24 29 32 37 40 45
PBLK
OBCLP
CLPDM
ID
WEN
CXD2470R
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
965
- 30 -
V3B
V4
1 4 5 8 13 16 21 24 29 32 37 40
Chart-10 Frame mode
* ICX202/ICX232
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
(1560) 0 50 100 150 200 250
HDI
MCKO
55 242
H1
H2
75 135
V1A/B
115 175
V2
55 155
V3A/B
95 195
V4
95 155
- 31 -
55 50 115 115
SUB
270
PBLK
10
OBCLP
244 270
CLPDM
ID
WEN
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-8.
CXD2470R
Chart-11
* ICX202/ICX232
Horizontal Direction Timing Chart
MODE Quadruple-speed mode
Applicable CCD image sensor
(1560) 0 50 200 250 100 150
HDI
MCKO
55 242
H1
H2
55 175 95 135
V1A/B
75 115 155 195
V2
55 95 135 175
V3A/B
75 115 155 195
- 32 -
95 155 55 50 115 115
V4
SUB
270
PBLK
10
OBCLP
244 270
CLPDM
ID
WEN
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-9.
CXD2470R
Chart-12
* ICX202/ICX232
Horizontal Direction Timing Chart (High-speed sweep: G)
MODE Frame mode
Applicable CCD image sensor
(1560) 0 50 100 150 200 250
HDI
MCKO
55 242
H1
H2
55 95 135 175 215 255
V1A/B
75 115 155 195 235 275
V2
55 175 95 135 215 255
V3A/B
75 115 155 195 235 275
V4
95
- 33 -
#1
155 55 50
#2
#3
SUB
PBLK
10
OBCLP
CLPDM
ID
WEN
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s). SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 33H of 1295ck (#659).
CXD2470R
Chart-13
* ICX202/ICX232
Horizontal Direction Timing Chart
MODE Frame mode
Applicable CCD image sensor
(1560) 0 843 903 923 983 (1560) 0
55 75 95 115 135 155 175 195
55 75 95 115 135 155 175 195
HDI [E]
[A Field]
V1A
V1B
V2
V3A
V3B
- 34 -
[F]
V4
[B Field]
V1A
V1B
V2
V3A
V3B
V4
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s).
CXD2470R
Chart-14
* ICX202/ICX232
Horizontal Direction Timing Chart
MODE Quadruple-speed mode
Applicable CCD image sensor
(1560) 0 843 903 923 983 (1560) 0
55 75 95 115 135 155 175 195
55 75 95 115 135 155 175 195
HDI [H]
V1A
V1B
V2
- 35 -
V3A
V3B
V4
The HDI of this chart indicates the actual CXD2470R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI. The HDI fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4s).
CXD2470R
Chart-15
* ICX224/ICX284/ICX202/ICX232
High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
HDI
HDI'
CKI
CKO
ADCLK
55/56 188/242
1
MCKO
- 36 -
H1
H2
RG
XSHP
XSHD
XRS
CXD2470R
HDI' indicates the HDI which is the actual CXD2470R load timing. The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. The logical phase of ADCLK can be specified by the serial interface.
CXD2470R
Application Circuit Block Diagram
CCD ICX224/ICX284 ICX202/ICX232 DRVOUT VRT VRB OBCLP
CCD OUT
S/H CXA2006Q CLPDM
A/D CXD2311AR ADCLK
D0 to 9 10
XSHD
XSHP
PBLK
XRS
H1 H2 RG V1A V1B V2 V3A V3B V4 SUB
16 17 18 19 20 22 12 13 9 41 43 39 44 46 40 47 26 27 28 37 48 V-Dr TG CXD2470R
23 25 30 34 35 4 5 2 3 6 31 32 33 CKO MCKO VDI HDI ID WEN Signal Processor Block 15.0V 0V -7.5V
RST DSGAT EBCKSM
CKI OSCO
TEST1
TEST2
OSCI
SCK
SEN
SSI
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on Of the three -7.5V, +15.0V and +3.3V power supplies, be sure to start up the -7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
t1
20%
20%
t2 t2 t1
- 37 -
CXD2470R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.5 0.2
S
(0.127) +0.05 0.127 - 0.02
(0.18)
0.18 0.03
0 to 10
0.5 0.2
DETAIL B:SOLDER DETAIL A
DETAIL B:PALLADIUM
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
- 38 -
0.127 0.04
+ 0.08 0.18 - 0.03

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